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| PRELIMINARY PRODUCT INFORMATION MOS INTEGRATED CIRCUIT PD161620 432 OUTPUT TFT-LCD SOURCE DRIVER WITH RAM DESCRIPTION The PD161620 is a TFT-LCD source driver that includes display RAM. This driver has 432 outputs, a display RAM capacity of 304,128 bits (432 dots x 4 bits x 176 lines) and, can provide a 4,096-color display. FEATURES * TFT-LCD driver with on-chip display RAM * Logic supply voltage: 2.5 to 3.6 V 5 * Driver supply voltage: 3.6 to 5.5 V * Display RAM: 432 x 4 x 176 bits 5 * Driver outputs: 432 output * CPU interface: Serial, 4-bit/8-bit parallel interface selectable 5 (Parallel interface requires WAIT control via RDY signal) * Colors: 4,096 colors/pixel * On-chip VCOM generator * On-chip timing generator * On-chip oscillator ORDERING INFORMATION Part Number Package TCP/Chip PD161620 Remark Purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representatives. The information contained in this document is being issued in advance of the production cycle for the device. The parameters for the device may change before final production or NEC Corporation, at its own discretion, may withdraw the device prior to its production. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14797EJ3V7PM00 (3rd edition) Date Published July 2001 NS CP(K) Printed in Japan The mark 5 shows the major revised points. (c) 2000 PD161620 5 1. BLOCK DIAGRAM Y1 Y2 Y3 Y4 Y431 Y432 LCD drive circuit Gray scale generator VRH, V0 to V15 VLH1, VLH2 Decoder Level shifter (2.7 V Display data latch 4 or 5 V) LCD timing control Display data RAM (4 x 176 x 144 x 3 bits) Calibrator Oscillator Arbiter BGR Internal timing generator Command decoder Address decoder / controller Data register VCOM generator I/O buffer Gate control PS control RS /CS1 CS2 /RD(E) /WR(R, /W) D7(SI) D6(SCL) D5(SO) D0 to D4 PSX0 PSX1 /RESET C86 RDY IP0 to IP3 OP0 to OP3 DCON RGONP VCE VCD2 VCD11 VCD12 LPMG,LPMP GCLK GSTB GOE1 GOE2 RGONG TEST10 VCOUT VCOMR BGRIN VSS VS DVCC1 VCC1 VCC2 Remark 2 /xxx indicates active low signal. Preliminary Product Information S14797EJ3V7PM TEST2 to TEST5, TESTIN TEST1, TEST6 to TEST9, TESTOUT OSCIN OSCSEL VCOM DVSS PD161620 5 2. PIN CONFIGURATION (PAD LAYOUT) Chip size: 16800 x 3060 m2 Bump size (output): 33 x 60 m2 Bump size (input & dummy): 87 x 60 m2 Alignment Mark X: -7806.06 Y: 858.24 X: 7783.83 Y: -914.43 389 390 Output side 338 outputs 50 49 Output side X(+ 438 439 72 um 60 um Input side 552 Output side 47 outputs Chip surface (Bump side) Y(- 1 72 um 60 um 72 um 72 um Preliminary Product Information S14797EJ3V7PM 3 PD161620 5 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pad name DUMMY Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 Y42 Y43 Y44 Y45 Y46 Y47 DUMMY DUMMY Y48 Y49 Y50 Y51 Y52 Y53 Y54 Y55 Y56 Y57 Y58 Y59 Y60 Y61 Y62 Y63 Y64 Y65 Y66 Y67 Y68 Y69 Y70 Y71 Y72 Y73 Y74 Y75 Y76 Y77 X[m] 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8287.08 8166 8088 8040 7992 7944 7896 7848 7800 7752 7704 7656 7608 7560 7512 7464 7416 7368 7320 7272 7224 7176 7128 7080 7032 6984 6936 6888 6840 6792 6744 6696 Table 2-1. Pad Layout (1/4) Y[m] -1182 -1104 -1056 -1008 -960 -912 -864 -816 -768 -720 -672 -624 -576 -528 -480 -432 -384 -336 -288 -240 -192 -144 -96 -48 0 48 96 144 192 240 288 336 384 432 480 528 576 624 672 720 768 816 864 912 960 1008 1056 1104 1182 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 Pad No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pad name Y78 Y79 Y80 Y81 Y82 Y83 Y84 Y85 Y86 Y87 Y88 Y89 Y90 Y91 Y92 Y93 Y94 Y95 Y96 Y97 Y98 Y99 Y100 Y101 Y102 Y103 Y104 Y105 Y106 Y107 Y108 Y109 Y110 Y111 Y112 Y113 Y114 Y115 Y116 Y117 Y118 Y119 Y120 Y121 Y122 Y123 Y124 Y125 Y126 Y127 Y128 Y129 Y130 Y131 Y132 Y133 Y134 Y135 Y136 Y137 Y138 Y139 Y140 Y141 Y142 Y143 Y144 Y145 Y146 Y147 Y148 Y149 Y150 Y151 Y152 Y153 Y154 Y155 Y156 Y157 X[m] 6648 6600 6552 6504 6456 6408 6360 6312 6264 6216 6168 6120 6072 6024 5976 5928 5880 5832 5784 5736 5688 5640 5592 5544 5496 5448 5400 5352 5304 5256 5208 5160 5112 5064 5016 4968 4920 4872 4824 4776 4728 4680 4632 4584 4536 4488 4440 4392 4344 4296 4248 4200 4152 4104 4056 4008 3960 3912 3864 3816 3768 3720 3672 3624 3576 3528 3480 3432 3384 3336 3288 3240 3192 3144 3096 3048 3000 2952 2904 2856 Y[m] 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 4 Preliminary Product Information S14797EJ3V7PM PD161620 5 Pad No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Pad name Y158 Y159 Y160 Y161 Y162 Y163 Y164 Y165 Y166 Y167 Y168 Y169 Y170 Y171 Y172 Y173 Y174 Y175 Y176 Y177 Y178 Y179 Y180 Y181 Y182 Y183 Y184 Y185 Y186 Y187 Y188 Y189 Y190 Y191 Y192 Y193 Y194 Y195 Y196 Y197 Y198 Y199 Y200 Y201 Y202 Y203 Y204 Y205 Y206 Y207 Y208 Y209 Y210 Y211 Y212 Y213 Y214 Y215 Y216 Y217 Y218 Y219 Y220 Y221 Y222 Y223 Y224 Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y233 Y234 Y235 Y236 Y237 X[m] 2808 2760 2712 2664 2616 2568 2520 2472 2424 2376 2328 2280 2232 2184 2136 2088 2040 1992 1944 1896 1848 1800 1752 1704 1656 1608 1560 1512 1464 1416 1368 1320 1272 1224 1176 1128 1080 1032 984 936 888 840 792 744 696 648 600 552 504 456 408 360 312 264 216 168 120 72 24 -24 -72 -120 -168 -216 -264 -312 -360 -408 -456 -504 -552 -600 -648 -696 -744 -792 -840 -888 -936 -984 Table 2-1. Pad Layout (2/4) Y[m] 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 Pad No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Pad name Y238 Y239 Y240 Y241 Y242 Y243 Y244 Y245 Y246 Y247 Y248 Y249 Y250 Y251 Y252 Y253 Y254 Y255 Y256 Y257 Y258 Y259 Y260 Y261 Y262 Y263 Y264 Y265 Y266 Y267 Y268 Y269 Y270 Y271 Y272 Y273 Y274 Y275 Y276 Y277 Y278 Y279 Y280 Y281 Y282 Y283 Y284 Y285 Y286 Y287 Y288 Y289 Y290 Y291 Y292 Y293 Y294 Y295 Y296 Y297 Y298 Y299 Y300 Y301 Y302 Y303 Y304 Y305 Y306 Y307 Y308 Y309 Y310 Y311 Y312 Y313 Y314 Y315 Y316 Y317 X[m] -1032 -1080 -1128 -1176 -1224 -1272 -1320 -1368 -1416 -1464 -1512 -1560 -1608 -1656 -1704 -1752 -1800 -1848 -1896 -1944 -1992 -2040 -2088 -2136 -2184 -2232 -2280 -2328 -2376 -2424 -2472 -2520 -2568 -2616 -2664 -2712 -2760 -2808 -2856 -2904 -2952 -3000 -3048 -3096 -3144 -3192 -3240 -3288 -3336 -3384 -3432 -3480 -3528 -3576 -3624 -3672 -3720 -3768 -3816 -3864 -3912 -3960 -4008 -4056 -4104 -4152 -4200 -4248 -4296 -4344 -4392 -4440 -4488 -4536 -4584 -4632 -4680 -4728 -4776 -4824 Y[m] 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 Preliminary Product Information S14797EJ3V7PM 5 PD161620 5 Pad No. 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 Pad name Y318 Y319 Y320 Y321 Y322 Y323 Y324 Y325 Y326 Y327 Y328 Y329 Y330 Y331 Y332 Y333 Y334 Y335 Y336 Y337 Y338 Y339 Y340 Y341 Y342 Y343 Y344 Y345 Y346 Y347 Y348 Y349 Y350 Y351 Y352 Y353 Y354 Y355 Y356 Y357 Y358 Y359 Y360 Y361 Y362 Y363 Y364 Y365 Y366 Y367 Y368 Y369 Y370 Y371 Y372 Y373 Y374 Y375 Y376 Y377 Y378 Y379 Y380 Y381 Y382 Y383 Y384 Y385 DUMMY DUMMY Y386 Y387 Y388 Y389 Y390 Y391 Y392 Y393 Y394 Y395 X[m] -4872 -4920 -4968 -5016 -5064 -5112 -5160 -5208 -5256 -5304 -5352 -5400 -5448 -5496 -5544 -5592 -5640 -5688 -5736 -5784 -5832 -5880 -5928 -5976 -6024 -6072 -6120 -6168 -6216 -6264 -6312 -6360 -6408 -6456 -6504 -6552 -6600 -6648 -6696 -6744 -6792 -6840 -6888 -6936 -6984 -7032 -7080 -7128 -7176 -7224 -7272 -7320 -7368 -7416 -7464 -7512 -7560 -7608 -7656 -7704 -7752 -7800 -7848 -7896 -7944 -7992 -8040 -8088 -8166 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 Table 2-1. Pad Layout (3/4) Y[m] 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1417.08 1182 1104 1056 1008 960 912 864 816 768 720 672 Pad No. 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 Pad name Y396 Y397 Y398 Y399 Y400 Y401 Y402 Y403 Y404 Y405 Y406 Y407 Y408 Y409 Y410 Y411 Y412 Y413 Y414 Y415 Y416 Y417 Y418 Y419 Y420 Y421 Y422 Y423 Y424 Y425 Y426 Y427 Y428 Y429 Y430 Y431 Y432 DUMMY DUMMY DUMMY TEST10 LPMG RGONG GOE2 GOE1 GCLK GSTB DVCC1 IP3 IP2 IP1 IP0 DVSS OP3 OP2 OP1 OP0 DUMMY VRL2 VRL1 V15 V14 V13 V12 V11 V10 V9 V8 V7 V6 V5 V4 V3 V2 V1 V0 VRH DUMMY TEST6 DVCC1 X[m] -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8287.08 -8204.46 -8060.46 -7916.46 -7772.46 -7628.46 -7484.46 -7340.46 -7196.46 -7052.46 -6908.46 -6764.46 -6620.46 -6476.46 -6332.46 -6188.46 -6044.46 -5900.46 -5756.46 -5612.46 -5468.46 -5324.46 -5180.46 -5036.46 -4892.46 -4748.46 -4604.46 -4460.46 -4316.46 -4172.46 -4028.46 -3884.46 -3740.46 -3596.46 -3452.46 -3308.46 -3164.46 -3020.46 -2876.46 -2732.46 -2588.46 -2444.46 -2300.46 Y[m] 624 576 528 480 432 384 336 288 240 192 144 96 48 0 -48 -96 -144 -192 -240 -288 -336 -384 -432 -480 -528 -576 -624 -672 -720 -768 -816 -864 -912 -960 -1008 -1056 -1104 -1182 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 6 Preliminary Product Information S14797EJ3V7PM PD161620 5 Pad No. 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 Table 2-1. Pad Layout (4/4) Pad name DVSS BGRIN VCOMR VS VS VS VSS VSS VSS VCC1 VCC1 VCC1 DUMMY DUMMY DUMMY VCOM VCOUT DUMMY DCON RGONP LPMP VCD11 VCD12 VCD2 VCE TESTOUT TESTIN DUMMY VCC2 VCC2 VCC2 CS2 DUMMY /RD(E) /WR(R,/W) RS D0 D1 D2 D3 D4 D5(SO) D6(SCL) D7(SI) /CS1 /RESET RDY OSCIN DVSS DUMMY DVCC1 PSX1 DVSS PSX0 DVCC1 C86 DVSS OSCSEL DVCC1 TEST5 TEST4 DVSS TEST3 DVCC1 TEST2 DVSS TEST1 TEST9 TEST8 TEST7 DUMMY DUMMY X[m] -2156.46 -2012.46 -1868.46 -1724.46 -1580.46 -1436.46 -1292.46 -1148.46 -1004.46 -860.46 -716.46 -572.46 -428.46 -284.46 -140.46 3.54 147.54 291.54 435.54 579.54 723.54 867.54 1011.54 1155.54 1299.54 1443.54 1587.54 1731.54 1875.54 2019.54 2163.54 2307.54 2451.54 2595.54 2739.54 2883.54 3027.54 3171.54 3315.54 3459.54 3603.54 3747.54 3891.54 4035.54 4179.54 4323.54 4467.54 4611.54 4755.54 4899.54 5043.54 5187.54 5331.54 5475.54 5619.54 5763.54 5907.54 6051.54 6195.54 6339.54 6483.54 6627.54 6771.54 6915.54 7059.54 7203.54 7347.54 7491.54 7779.54 7779.54 7923.54 8204.46 Y[m] -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 -1417.08 Preliminary Product Information S14797EJ3V7PM 7 PD161620 3. PIN FUNCTIONS 3.1 Power Supply System Pins Symbol VCC1 VCC2 VS VSS Pin Name Logic power supply pin I/O power supply pin Ground pin Power supply for -curve correction Pad No. 490 to 492 509 to 511 487 to 489 476 to 461 477, 460, 459 I/O Function Power supply pin for logic circuit Power supply pin for I/O buffer Power supply pin for driver circuit Ground pin for logic and driver circuits The PD161620 includes power supplies and resistors for the -curve, so if the characteristics of the -curve and LCD panel in the PD161620 match, leave V0 to V15, VRH, VRL1, VRL2 open. If some kind of correction is required, adjust the -curve by connecting resistors between the V0 to V15, VRH, VRL1, VRL2 pins (see 5.9 -Curve Correction Power Supply Circuit for Cases of Unbalanced Driving). Pull-up power-supply pin for mode setting Pull-down power-supply pin for mode setting Driver power supply pin 484 to 486 5 V0 to V15 VRH VRL1, VRL2 5 DVCC1 5 DVSS Mode setting pull-up power-supply pin 448,480,531, 535,539,544 - Mode setting pull-down 453,481,529, power-supply pin 533,537,542, 546 3.2 Logic System Pins Symbol Pin Name Pad No. I/O Function PSX0, PSX1 CPU interface selection 534, 532 Input These pins are used to select the CPU interface mode. PSX0 = H: 8-bit parallel interface PSX0 = L: 4-bit parallel interface PSX1 = H: Parallel interface PSX1 = L: Serial interface Input This pin is used for chip select signals. When /CS1 = L (CS2 = H), (1/3) /CS1, CS2 /RD (E) Chip select 525, 512 the chip is active and can perform data input/output operations including command and data I/O. Input When i80 series parallel data transfer (/RD) has been selected, the signal at this pin is used to enable read operations. Data is output to the data bus only when this pin is low. When M68 series parallel data transfer (E) has been selected, the signal at this pin is used to enable read/write operations. Read (enable) 514 5 /WR (R, /W) Write(read/write) 515 Input When i80 series parallel data transfer (/WR) has been selected, the signal at this pin is used to enable write operations. Data is written at the rising edge of this signal. When M68 series parallel data transfer (R, /W) and serial data has been selected, this pin is used to determine the direction of data transfer. L: Write H: Read C86 Select interface 536 Input This pin is used to switch between interface modes (i80 series CPU or M68 series CPU). L: Selects i80 series CPU mode H: Selects M68 series CPU mode 8 Preliminary Product Information S14797EJ3V7PM PD161620 (2/3) Symbol Pin Name Ready signal Pad No. 527 I/O Function connect this pin to external WAIT pin of the CPU. When in serial mode, this pin is not used, so leave it open. 5 RDY Output This pin is the ready signal output. When in 4-bit or 8-bit parallel mode, 5 D0 to D7 (SI) (SO) (SCL) Data bus (Serial data Input) (Serial data output) (Serial clock) 517 to 524 I/O These pins comprise 8-bit bi-directional data. When the serial interface has been selected (PSX1 = L ), D7 functions as a serial data input pin (SI), D6 functions as a serial clock input pin (SCL), and D5 functions as a serial data output pin (SO). In either case, pins D0 to D4 are in high impedance mode. When the chip is not selected, D0 to D7 are in high impedance mode. 5 RS Index register/data, command selection 516 Input When parallel data transfer has been selected, this pin is usually connected to the LSB of the standard CPU address bus and is used to distinguish between data from index registers and data/commands. RS = H: Indicates that data from D0 to D7 is data/command RS = L: Indicates that data from D0 to D7 is index register contents Also, when serial data transfer is selected, the level of the RS pin is fetched at the rising edge of the eighth clock of the serial clock and whether the data is index register contents or data/command is distinguished. RS = H: Indicates that the data input to SI is data/command. RS= L: Indicates that the data input to SI is index register contents. TESTOUT /RESET Test output Reset 506 526 Output This test output pin is used when the IC is in test mode, otherwise, it is left unconnected. Input When /RESET is low, an internal reset is performed. The reset operation is executed at the /RESET signal level. Be sure to perform reset via this pin at power application. 5 TEST4, TEST5 TEST2, TEST3 Test 540, 541 545, 543 Input Input low level. 5 IP0 to IP3 Input port 452 to 449 Input This is a general-purpose input port. The status of these pins (H or L) can be read via a command. Because this is CMOS input, do not leave these pins open. 5 OP0 to OP3 5 TEST6 5 TEST1 5 TEST10 5 LPMG 5 LPMP 5 GOE1 Output port Test 457 to 459 479 547 441 Output This is a general-purpose output port. The status of these pins (H or L) can be write via a command. Output Leave open. Connect this pin to the SB pin of the gate driver. Output This is an output pin for low power mode (for the gate driver). Connect this pin to the LPM pin of the gate driver. This is an output pin for the low power mode (for the power-supply IC). Connect this pin to the LPM pin of the power-supply IC. Output This pin is an output pin for the low power mode (for the OE1). Connect to the OE1 pin of the gate driver. For the signal output timing, refer to 5.4 Display Timing Generator. Low power mode signal 442 501 OE1 output for gate driver 445 5 GOE2 OE2 output for gate driver 444 Output This pin is the OE2 output for the gate driver. Connect to the OE2 pin of the gate driver. For the signal output timing, refer to 5.4 Display Timing Generator. Preliminary Product Information S14797EJ3V7PM 9 PD161620 (3/3) Symbol Pin Name STB output for gate driver Pad No. 447 I/O Function 5 GSTB Output This pin is the STB output for the gate driver. Connect to the STVR or STVL pin of the gate driver. For the signal output timing, refer to 5.4 Display Timing Generator. GCLK CLK output for gate driver 446 Output This pin is the CLK output for the gate driver. Connect this pin to the CLK pin of the gate driver. 5 5 5 5 5 5 DCON DC/DC converter control 499 Output DC/DC converter ON/OFF control of power supply IC Connect this pinto the DCON pin of the power-supply IC. RGONP Regulator control 500 Output Regulator ON/OFF control of power supply IC Connect this pin to the RGONP pin of the power-supply IC. RGONG Regulator control 443 Output Regulator ON/OFF control of gate driver IC Connect this pin to the RGONG pin of the gate driver. VCD11, VCD12 VDD1 booster select 502, 503 Output Control signal to select x4/x5/x6/x7 booster of power supply IC for VDD1. Connect this pin to the VCD11 and VCD12 pins of the power-supply IC. VCD2 VDD2 booster select 504 Output Control signal to select x2/x3 booster of power supply IC for VDD2. Connect this pin to the VCD2 pin of the power-supply IC. VCE VO level select 505 Output Signal for selecting the level of the power supply IC booster voltage, to be used for the maximum voltage of VO. Selects that the booster voltage level is either the same level as VDD1 or a multiple of minus 1. Connect this pin to the VCE pin of the power-supply IC. 5 5 5 5 TEST7 TEST8 TEST9 OSCIN Test 550 549 548 I/O I/O I/O Input Leave open. Oscillation signal pins 528 This pin is for oscillation signal input. OSCIN = H: Input oscillation signal OSCIN = L: This pin is left open. OSCSEL Oscillation signal select 538 Input This pin is the oscillation signal select. When an external oscillation circuit is used, set this pin to H. When an internal oscillation circuit is used, set this pin to L. 5 BGRIN 5 VCOMR 5 TESTIN External-power-supply connection pin VCOM setting resistor connection pin Test input pins 482 483 Input This is an external-power-supply input pin for VCOM. For more detail, refer to 5.5 Common Adjustment Circuit. Input Connects an external resistor for VCOM setting. For more detail, refer to 5.5 Common Adjustment Circuit. 507 Input These pins are used to set a test mode for the IC. Normally, this setting is open. 10 Preliminary Product Information S14797EJ3V7PM PD161620 3.3 Driver-Related Pins Symbol Y1 to Y432 Pin Name Source output Pad No. 2 to 48, 51 to 388, 391 to 519 I/O Output Source output pins Function 5 VCOM 5 VCOUT COM center voltage adjustment Center rectangle signal output 514 Output This pin is the common center voltage adjustment output. For more detail, refer to 5.5 Common Adjustment Circuit. 515 Output This pin is the center rectangle signal output (4 Vp-p or 5 Vp-p) for common modulation. For more detail, refer to 5.5 Common Adjustment Circuit. DUMMY Dummy pin 1, 49, 50, 389, 390, 438 to 441, 449, 477 to 480, 498 to 500, 524, 541, 546 to 552 Dummy pin Preliminary Product Information S14797EJ3V7PM 11 PD161620 5 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS The I/O circuit types of each pin and recommended connection of unused pins are described below. Power supply VCC1 VCC2 VCC2 VCC1 VCC2 VCC2 VCC2 VCC2 VCC2 VCC1 VCC2 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC1 VCC2 VCC1 VS VS VS VS Recommended Connection of Unused Pins Parallel Interface Mode setting pinNote Connect to VCC2 Connect to VCC2 (when i80 series interface) Mode setting pinNote Leave open Always reset on power application Connect to VCC1 or VSS1. Leave open Leave open Leave open Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Always connect to the gate driver Always connect to the power IC Always connect to the power IC Always connect to the gate driver Always connect to the power IC Always connect to the power IC Always connect to the power IC Leave open Connect to VSS Connect to VSS Connect to VSS Connect to VSS Leave open Leave open Leave open Leave open Leave open (in OSCSEL = L mode) Mode setting pinNote Connect to VSS (in BGRS = L mode) Connect to VSS Leave open Leave open Connect to VCC2 or VSS Connect to VCC1 or VSSNote Leave open Leave open Serial Interface Pin Name PSX0, PSX1 CS2 /RD(E) C86 RDY D0 to D4 D5 (SO) D6 (SCL) D7 (SI) TESTOUT /RESET IP0 to IP3 OP0 to OP3 TEST10 LPMG, LPMP GOE1 GOE2 GSTB GCLK DCON RGONP RGONG VCD11, VCD12 VCD2 VCE TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 OSCIN OSCSEL BGRIN VCOMR VCOM VCOUT Input Type Schmitt trigger Filter Filter Schmitt trigger Filter Filter Filter Filter Filter Schmitt trigger CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Schmitt trigger - I/O Input Input Input Input Output I/O I/O I/O I/O Output Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Output Output Output Output Input Input Input Input Output Output Note Connect to VCC1 or VSS, depending on the mode selected. 12 Preliminary Product Information S14797EJ3V7PM PD161620 5. DESCRIPTION OF FUNCTIONS 5.1 CPU interface 5.1.1 Selection of interface type The PD161620 chip transfers data using an 8-bit bidirectional data bus (D7 to D0), 4-bit bi-directional data bus (D7 5 to D4) or a serial data input (SI) or a serial date output (SO). Setting the polarity of the PSX0-1 pins as either H (high) or L (low) enables the selections shown in Table 5-1 below. 5 PSX1 Table 5-1. PSX0 H L X Note2 Mode 8-bit parallel 4-bit parallel serialNote3 /CS1 /CS1 /CS1 /CS1 RDY RDY RDY Hi-ZNote1 RS RS RS RS /RD (E) /RD (E) /RD (E) Note2 /WR (R, /W) /WR (R, /W) /WR (R, /W) /WR (R, /W) C86 C86 C86 Note2 D7 D7 D7 SI D6 D6 D6 SCL D5 D5 D5 SO D4 D4 D4 Hi-ZNote1 D3 to D0 D3 to D0 Hi-ZNote1 Hi-ZNote1 H H L 5 5 Notes 1. Hi-Z: High impedance 2. X: Don't care (H or L) 3. In serial mode, only commands can be read. Internal RAM data cannot be read. 5.1.2 Selection of data transfer mode In the PD161620, when the 8-bit parallel interface and serial interface are selected, there are tow types of modes to transfer data to display RAM. The mode can be selected as follows with the DTX command. In the 1-pixel/2-byte mode, 1 pixel of data is written at one time to the internal RAM each time 2 bytes of data are transferred. If only 1 byte of data has been transferred, writing to the internal RAM is not possible. Similarly, in the 2pixel/3-byte mode, 2 pixels of data are written at one time to the internal RAM each time 3 bytes of data are transferred. Execute data transfer taking into consideration the above. Table 5-2. DTX 1 0 1-pixel / 2-byte 2-pixel / 3-byte Mode 5 Caution In the 4-bit parallel mode, the DTXX command is disabled. One pixel gets written by transferring 4 bits of data 3 times. The transfer order and relationship between command data and display data are as follows. Preliminary Product Information S14797EJ3V7PM 13 PD161620 Figure 5-1. Correspondence Between Data Bus and Display RAM (When DTX = 1) Data bus side DB7 DB6 DB5 1st byte DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 2nd byte DB4 DB3 DB2 DB1 DB0 D11 D10 D9 Dot 1 D8 D7 D6 D5 Dot 2 1st pixel D4 D3 D2 D1 Dot 3 D0 x x x x Invalid data Display RAM side Figure 5-2. Correspondence Between Data Bus and Display RAM (When DTX = 0) Data bus side DB7 DB6 DB5 1st byte DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 2nd byte DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 3rd byte DB4 DB3 DB2 DB1 DB0 D11 D10 D9 Dot 1 D8 D7 D6 D5 Dot 2 1st pixel D4 D3 D2 D1 Dot 3 D0 D11 D10 D9 Dot 1 D8 D7 D6 D5 Dot 2 2nd pixel D4 D3 D2 D1 Dot 3 D0 Display RAM side 5.1.3 Parallel interface When the parallel interface has been selected (PSX1 = H), setting the C86 pin as either H or L enables a direct 5 connection to an i80 series or M68 series CPU (see table below). When the parallel interface is used, wait control for the bus is required. To execute wait control, connect the RDY pin to the external WAIT pin of the CPU. Table 5-3. C86 H L Mode M68 series CPU i80 series CPU /RD(E) E /RD /WR(R, /W) R, /W /WR The data bus signal is identified according to the combination of the RS, /RD(E), and /WR(R,/W) signals, as shown in the following table. Table 5-4. Common RS H H L L M68 series CPU R, /W H L H L i80 series CPU /RD L H L H /WR H L H L Read display data and registers Write display data and registers Prohibited Write to control index register Function 14 Preliminary Product Information S14797EJ3V7PM PD161620 (1) i80 Series Parallel Interface When i80 series parallel data transfer has been selected, data is written to the PD161620 at the rising edge of the /WR signal. The data is output to the data bus when the /RD signal is L. Figure 5-3. i80 Series Interface Data Bus Status /CS1 (CS2 = H) /WR /RD Hi-Z DBn Data write Valid data Data read Hi-Z (2) M68 Series Parallel Interface When M68 series parallel data transfer has been selected, data is written at the falling edge of the E signal when the R,/W signal is L. In a data read operation, data is output at the rising edge of the E signal in a period when the R,/W signal is H. The data bus is released (Hi-Z) at the falling edge of the E signal. Figure 5-4. M68 Series Interface Data Bus Status (When data read) /CS1 (CS2 = H) R,/W E Hi-Z DBn Valid data Hi-Z Preliminary Product Information S14797EJ3V7PM 15 PD161620 5 5.1.4 Serial interface When the serial interface has been selected (PSX = L), if the chip is active (/CS1 = L, CS2 = H), serial data input (SI), serial data output (SO), and serial clock input (SCL) can be received. Serial data is read from D7 and then from D6 to D0 on the rising edge of the serial clock, via the serial input pin. This data is synchronized on the eighth serial clock's rising edge and is then converted to parallel data for processing. Also, set /WR = L during write and /WR = H during read. Note that in the 1-pixel/2-byte mode, make /CS1 active (/CS1 = L) during transfer of 1pixel of data (2 bytes). Similarly in the 2-pixel/3-byte mode, make CS1 active (/CS1 = L) during transfer of 2 pixels of data (3 bytes). IF /CS1 = H is set during data transfer, the data may not be transferred normally. RS input is used to judge serial input data as display data or command data when RS = H the data is display data and when RS = L the data is command data. When the chip enters active mode, RS input is read at the rising edge after every eighth serial clock and is then used to judge the serial input data. The serial interface signal chart is shown below. 5 CS2 = "H" /CS1 SI SCL RS /WR (When in data writing) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 Figure 5-5. Serial Interface Signal Chart 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Remarks 1. If the chip is not active, the shift register and counter are reset to their initial settings. 5 2. The data read function is disabled during serial interface mode (command register is enabled). 3. When using SCL wiring, take care concerning the possible effects of terminating reflection and noise from external sources. Our recommends checking operation with the actual device. 5.1.5 Chip select The PD161620 has two chip select pins (/CS1 and CS2). The CPU parallel and serial interfaces can be used only when /CS1 = L and CS2 = H. When the chip select pin is inactive, D0 to D7 are set to high impedance (invalid) and input of RS, /RD, or /WR is not active. If a serial interface mode has been set, the shift register and counter are both initialized. 5 Note that when using the serial interface, in the 1-pixel/2-byte mode, /CS1 must be made active (/CS1 =L) during transfer of 1 pixel of data (2 bytes). Similarly in the 2-pixel/3-byte mode, /CS1 must be made active (/CS1 = L) during transfer of 2 pixels of data (3 bytes). If /CS1 = H is set during data transfer, the data may not be transferred normally. However, if the parallel interface is used, transfer is performed normally as long as /CS1 is active only during data transfer in 1-byte units, regardless of whether the 1-pixel/2-byte mode or the 2-pixel/3-byte mode is selected. 16 Preliminary Product Information S14797EJ3V7PM PD161620 5 5.1.6 Wait control in parallel interface mode When the parallel interface mode is selected, wait control for the bus is required. Connect the RDY pin of the PD161620 to the external WAIT pin of the CPU to execute wait control. An example of the connection to the CPU is described in 10. EXAMPLE of PD161620 and CPU CONNECTION. Note that when serial interface mode is selected, wait control via the RDY signal is not required. 5.2 Display Data RAM This is the RAM that is used to store the display's dot data. The RAM configuration is 1,728 bits (144 x 12 bits) x 176 bits. Any specified pixel can be accessed by selecting the corresponding X address and Y address. Figure 5-6 shows the structure of display data RAM. Figure 5-6. D11 D10 Dot 1 D9 D8 D7 D6 Dot 2 One pixel ( = one X address) D5 D4 D3 D2 Dot 3 D1 D0 5.2.1 X address circuit As shown in Figure 5-7, the display data RAM's X address is specified via the X address register. When using the X address increment mode, the specified X address is incremented by one each time a display data read or write operation is executed. The CPU is able to continuously access the display data. Following incrementation up to the final X address, executing a display data read or write operation will cause the Y address to be incremented, and the X address to return to 000H. For the reset value of the address counter, see Table 5-6. It is also possible to invert the relationship between the X address and the source output using the ADX flag of control register 1, as shown in Figure 5-7. 5.2.2 Column address circuit When displaying the contents of the display data RAM, the column address corresponds to source output, as is shown Figure 5-7. As is shown in Table 5-5, the correspondence between the display RAM's column address and source output can be inverted using the ADC flag in control register 1 (source driver direction selection flag). This reduces the constraints on chip layout when assembling the LCD module. Table 5-5. Source Output ADC 0 1 Y1 000H 1AFH Y2 001H 1AEH Column address Column address Y431 1AEH 001H Y432 1AFH 000H Preliminary Product Information S14797EJ3V7PM 17 PD161620 5 5.2.3 Y address circuit As is shown in Figure 5-7, the Y address register is used to specify the display data RAM's Y address. When using the Y address increment mode, the specified Y address is incremented by one each time a display data read or write operation is executed. The CPU is able to continuously access the display data. The Y address is incremented up to AFH, after which the X address is incremented after each read or write operation and the Y address is set back to 00H. In the case of the 8-bit parallel interface mode and serial interface mode, only the 1-pixel/2-byte mode can be used as the transfer mode. Table 5-6. Counter reset for RAM increment X-address 08FH Y-address AFH 5 ADM0=L,ADM1=L ADX=0 Source output ADC=0 ADC=1 X-address Column addres Figure 5-7. PD161620 RAM addressing Y1 Y432 000H D11---D8 Gate output R,/L=H R,/L=L O1 O2 | | O87 O88 O89 O90 | | O175 O176 O176 O175 | | O90 O89 O88 O87 | | O2 O1 Y-address 00H 01H | | 56H 57H 58H 59H | | AEH AFH Display area Y2 Y431 000H 001H D7---D4 1st Pixel Y3 Y430 002H D3---D0 Y4 Y429 003H D11---D8 Y5 Y428 001H 004H D7---D4 2nd Pixel Y6 Y427 005H D3---D0 ----------------1AAH D11---D8 Y427 Y6 Y428 Y5 08EH 1ABH D7---D4 1st Pixel Y429 Y4 1ACH D3---D0 Y430 Y3 1ADH D11---D8 Y431 Y2 08FH 1AEH D7---D4 2nd Pixel Y432 Y1 1AFH D3---D0 ADX=1 Source output ADC=0 ADC=1 X-address Column addr Gate output R,/L=H R,/L=L O1 O2 | | O87 O88 O89 O90 | | O175 O176 O176 O175 | | O90 O89 O88 O87 | | O2 O1 Y-address 00H 01H | | 56H 57H 58H 59H | | AEH AFH Display area 1AFH D11---D8 Y1 Y432 Y2 Y431 08FH 1AEH D7---D4 2nd Pixel Y3 Y430 1ADH D3---D0 Y4 Y429 1ACH D11---D8 Y5 Y428 08EH 1ABH D7---D4 1st Pixel Y6 Y427 1AAH D3---D0 --- ----- ----- ----- --005H D11---D8 Y427 Y6 Y428 Y5 001H 004H D7---D4 2nd Pixel Y429 Y4 003H D3---D0 Y430 Y3 002H D11---D8 Y431 Y2 000H 001H D7---D4 1st Pixel Y432 Y1 000H D3---D0 18 Preliminary Product Information S14797EJ3V7PM PD161620 5.3 Oscillator The PD161620 includes a CR-type oscillator, which generate the display clock. When OSCSEL is L, an internal oscillator is selected. When OSCSEL is H, the internal oscillator is stopped, making it necessary to input the clock from an external oscillator. This oscillator also has a calibration function. The time to select one line is set by the calibration start and stop commands. Figure 5-8. Frame Frequency Calibration Calibration command Start/Stop Register OSC N-bit counter Internal clock The calibration function involves counting the number of oscillation clocks generated between the start and stop signals and storing that number in a register. The number of oscillation clocks is then continually compared with this register value in subsequent operations, and the time of the clock number stored in the register is set as 1 line selection time, and used as the internal reference clock. Using this function allows the frame frequency to be held at a constant value, even when the oscillation frequency is irregular. Figure 5-9. Calibration Function Timing Calibration start tcal (1 line time) Calibration stop tcal = 1/(fFRAME x n) fFRAME = Frame frequency n: Line numbers 1 OSC1 2 3 4 5 6 7 1 OSC2 2 3 4 Preliminary Product Information S14797EJ3V7PM 19 PD161620 5 5.4 Display Timing Generator The display timing generator generates the timing signals for the internal timing of the source driver and for the gate driver. The output timings for normal operation, for normal operation standby mode, and for standby mode normal operation, are shown below. 5 Figure 5-10. During Normal Operation (during line inversion) GSTB Data output line No. GCLK GOE1 GOE2 Source output VCOUT Gate output O176 Gate output O1 Gate output O2 176 dummy 1 2 3 4 5 175 176 dummy 1 2 3 Internal oscillation clock GSTB GCLK GOE1 VCOUT Source output (Source follower buffer output) Gate output O1 Gate output O2 1st line 2nd line 20 Preliminary Product Information S14797EJ3V7PM PD161620 5 Figure 5-11. Normal Operation Standby Input (during line inversion) GSTB Data output line No. GCLK GOE1 GOE2 Source output VCOUT Gate output O176 Gate output O1 Gate output O2 Standby command execution Internal oscillation clock GSTB GCLK GOE1 GOE2 VCOUT Source output (source follower buffer output) Gate output O1 Gate output O2 176th line 176 dummy 1 2 3 4 5 175 176 dummy standby mode Display OFF Dummy line Standby mode Preliminary Product Information S14797EJ3V7PM 21 PD161620 5 Figure 5-12. Standby Return to Normal Operation (during line inversion) GSTB Data output line No. GCLK GOE1 GOE2 Source output standby mode 1 2 3 175 176 dummy 1 2 3 VCOUT Gate output O176 Gate output O1 Gate output O2 Internal oscillator clock GSTB GCLK GOE1 VCOUT Source output (source follower buffer output) Gate output O1 Gate output O2 1st line 2nd line Standby release 22 Preliminary Product Information S14797EJ3V7PM PD161620 5 5.5 Common Adjustment Circuit To generate common output, the center voltage of the common waveform is output from the VCOM pin along with output of a 0 to VS (V) square waveform from the VCOUT pin. The level of the VCOM output can be adjusted using as external resistor. Figure 5-13. Common Adjustment Circuit Outputs common center voltage Internal regulator output:1.24 TYP. (V) Set with command (D6 bit of R32 register) + - BGRIN VCOMR VCOM VCOUT VS(V) 0 (V) Output 0 to VS (V) square wave C1 R3 Output waveform to common R1 VS(V) R2 0 (V) Output waveform at VCOM output is VS/2 or lower The BCOM voltage formulas are shown below. Preliminary Product Information S14797EJ3V7PM 23 PD161620 5.6 Square Wave Signal Generation Circuit 5 This circuit generates a common square wave signal. A 0 to VS (V) square wave is output from the BCOUT pin. 5.7 Reference Voltage Generator The PD161620 has a reference voltage generator for the voltage regulator. 24 Preliminary Product Information S14797EJ3V7PM PD161620 5 5.8 -Curve Correction Power Supply Circuit for Cases of Unbalanced Driving The PD161620 includes a -curve correction power supply circuit for cases of unbalanced driving. If the internal curve correction matches the LCD characteristics, no external components are necessary. Support for unbalanced driving is also provided in this circuit using the resistor between VRL1 to VRL2 shown in the Figure 5-14. 5 Figure 5-14. -Curve Correction Circuit Negative polarity VS VRH VSS V0 , V0 (black) VSS Positive polarity VS V1 V1 , V2 V2 , V3 V3 , V4 V4 , V5 V5 , V6 V6 , V7 V7 , V8 V8 , V9 V9 , V10 V10 , V11 V11 , V12 V12 , V13 V13 , V14 V14 , V15 , V15 (white) VRL1 VS VS VRL2 VSS VSS Preliminary Product Information S14797EJ3V7PM 25 PD161620 5 Table 5-7. -Curve Correction Circuit When in VS = 5 V Resistance(k) Data 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH Dn+3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Dn+2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Dn+1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Dn 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0' V1' V2' V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 0.0 18.4 16.8 17.6 12.0 9.6 7.2 7.2 4.8 6.4 4.0 6.4 4.8 5.6 6.4 77.6 0.0 0.0 Negative Voltage (V) 0.000 0.449 0.859 1.289 1.582 1.816 1.992 2.168 2.285 2.441 2.539 2.695 2.813 2.949 3.105 5.000 Positive Voltage (V) 5.000 4.551 4.141 3.711 3.418 3.184 3.008 2.832 2.715 2.559 2.461 2.305 2.188 2.051 1.895 0.000 rTOTAL = 204.8 Data vs Driving Voltage 6.000 5.000 4.000 (V) 3.000 2.000 1.000 0.000 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH DATA Negative Voltage (V) Positive Voltage (V) 26 Preliminary Product Information S14797EJ3V7PM PD161620 5.9 Partial Display Mode The PD161620 is provided with a function that allows sections within the screen to be displayed separately (partial display mode). The start line of the area to be displayed in partial display mode is set using the partial display area start line register (R28, R29), the number of lines in the area to be displayed is set using the partial display area line number register (R30, 31), and the color of the area not to be displayed is set using the partial off area color register 5 (R27). If "1" is set in the partial display area line count registers (R30, R31), the partial display areas each become 1 line. If "0" is set, there are no partial display areas but only normal display areas. The non-display area indicated by R28 and R30 is called Partial 1, and the non-display area indicates by R29 and R31 is called Partial 2. The Partial 2 setting is enabled only when the Partial 1 setting has been performed (when R30 0). Therefore, to set only one area as a non-display area, perform only the setting for Partial 1. Low power consumption cannot be achieved if only the partial mode is set. If low power consumption is required, the mode must be switched to the 8-clor mode. Figure 5-15. Partial Display Mode 00H 01H 02H 03H ... 7DH 7EH 7FH Partial non-display start line Section not displayed Cautions 1. The "scroll step count register (R26)" command is ignored in the partial display mode. 5 2. The specified partial areas must not directly overlap, and the Partial 1 area and Partial 2 area must be separated by at least one line. If the areas overlap, only the Partial 1 settings are valid, and partial display is not performed for the Partial 2 area. 5 3. In the case of the 4096 mode, only "00H" can be set to the partial OFF area color register (R27). In the case of the 8-color mode, any value from 00H to 07h can be set. The following sequence is recommended to avoid display malfunction when switching from normal display mode to partial display mode and vice versa. Preliminary Product Information S14797EJ3V7PM 27 PD161620 (1) Recommended sequence for switching from normal display mode to partial display mode DISP = 0 R0 D6 D2 <1> Display off PGDn setting Display data overwrite (for partial display) R27 D0 <2> Partial off area color register setting Note 1 <3> Display data overwrite Note 1 D7 P1SLn, P2SLn setting R28, R29 D0 D7 <4> Partial display area start line setting Note 1 P1AWn, P2AWn setting DTY = 1, COLOR = 1 DISP = 1 R30, R31 D0 D1, D2 <5> Partial display area line number setting Note 1 R1 <6> Partial display mode, 8-color modeNote 2 R0 D6 <7> Display on Notes 1. <2> to <5> can be executed in any order. 2. <6> must be executed after <4> and <5> have been set. 28 Preliminary Product Information S14797EJ3V7PM PD161620 (2) Recommended sequence for switching from partial display mode to normal display mode DISP = 0 Display data overwrite (for normal display) DTY = 0, COLOR = 0 DISP = 1 R0 D6 <1> Display off <2> Display data overwrite Note R1 D1, D2 <3> Partial display mode, 4096-color modeNote R0 D6 <4> Display on Note <2> to <3> can be executed in any order. (3) Recommended sequence for switching from partial display mode to partial display mode (switching the partial display area) DISP = 0 (Display data overwrite) R0 D6 <1> Display off <2> Display data overwrite Notes Note 1, 2 D7 P1SLn, P2SLn setting R28, R29 D0 D7 <3> Partial display area start line setting Note 1 P1AWn, P2AWn setting DTY = 1 DISP = 1 R30, R31 R1 R0 D0 D1 D6 <4> Partial display area line number setting Note 1 <5> Partial display mode Note 3 <6> Display on Notes 1. <2> to <4> can be executed in any order. 2. Execute <2> only when necessary. 3. <5> must be executed after <3> and <4> have been set. Preliminary Product Information S14797EJ3V7PM 29 PD161620 (4) Partial display setting examples Setting A-1 Register Partial display area start line register (R28, R29) Partial display area line number register (R30, R31) Setting Value 00H 57H Details of Setting Value Sets Y address 00H Sets an area of 88 lines Setting A-2 Register Partial display area start line register (R28, R29) Partial display area line number register (R30, R31) Setting Value 58H 57H Details of Setting Value Sets Y address 58H Sets an area of 88 lines Setting A-3 Register Partial display area start line register (R28, R29) Partial display area line number register (R30, R31) Setting Value 84H 57H Details of Setting Value Sets Y address 84H Sets an area of 88 lines Setting A-4 Register Partial display area start line register (R28, R29) Partial display area line number register (R30, R31) Setting Value 2CH 57H Details of Setting Value Sets Y address 2CH Sets an area of 88 lines 30 Preliminary Product Information S14797EJ3V7PM PD161620 Figure 5-16. Partial Display Setting Examples Setting A-1 144 Gate 1 Source Gate 1 1 Source 1 Setting A-2 144 Partial display area Area not displayed 88 89 88 89 Area not displayed Partial display area 176 176 Source Gate 1 1 Setting A-3 144 Partial display area Gate Source 1 1 Setting A-4 144 Area not displayed 44 45 44 45 Area not displayed Partial display area 132 133 Partial display area 176 132 133 Area not displayed 176 Preliminary Product Information S14797EJ3V7PM 31 PD161620 5.10 Screen Scroll The PD161620 has a screen scroll function. Any area of the screen can be scrolled by using the scroll area start line register (R22), scroll area line count register (R24), and scroll step count register (R26) to set the Y address of the top line of the area to be scrolled, the number of lines of the area to be scrolled, and the scroll step number, respectively. Note that in partial mode, the screen scroll function is disabled. Table 5-8. Scroll Area Start Line Register (R22) SSL7 0 0 0 0 1 1 1 SSL6 0 0 0 0 0 0 0 SSL5 0 0 0 0 1 1 1 SSL4 0 0 0 0 0 0 0 SSL3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SSL2 0 0 0 0 SSL1 0 0 1 1 SSL0 0 1 0 1 Start Line Y Address 00H 01H 02H 03H ADH AEH AFH Table 5-9. Scroll Area Line Count Register (R24) SAW7 0 0 0 0 1 1 1 SAW6 0 0 0 0 0 0 0 SAW5 0 0 0 0 1 1 1 SAW4 0 0 0 0 0 0 0 SAW3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SAW2 0 0 0 0 SAW1 0 0 1 1 SAW0 0 1 0 1 Scroll Area Line Number 1 2 3 4 174 175 176 Table 5-10. Scroll Step count Register (R26) SST7 0 0 0 0 1 1 1 SST6 0 0 0 0 0 0 0 SST5 0 0 0 0 1 1 1 SST4 0 0 0 0 0 0 0 SST3 0 0 0 0 1 1 1 1 1 1 0 1 1 1 0 1 SST2 0 0 0 0 SST1 0 0 1 1 SST0 0 1 0 1 Scroll Step Number 0 (No scroll) 1 2 3 173 174 175 Scrolling must be set using the following sequence. 32 Preliminary Product Information S14797EJ3V7PM PD161620 (1) Recommended sequence D7 SSLn setting R22 D0 D7 <1> Scroll area start line setting Note 1 SAWn setting R24 D0 D7 <2> Scroll area line number setting Note 1 SSTn setting R26 D0 <3> Scroll step count register setting Note 2 Notes 1. <1> to <2> can be executed in any order. 2. <3> must be executed after <1> and <2> have been set. Remark Set SSTn to 00H to disable the scroll operation. No particular sequence is required for this. Cautions 1. If the sum of the values of SSLn and SAWn is 176 (AFH) or over, it is invalid (no scroll operation). 2. Set the step number SSTn so that it does not exceed the line number SAWn. If a value exceeding SAWn is set, it will be invalid (no scroll operation). Preliminary Product Information S14797EJ3V7PM 33 PD161620 (2) Scroll setting examples Setting A-1 Register Scroll area start line register (R22) Scroll area line count register (R24) Setting Value 00H AFH Details of Setting Value Sets Y address 00H Sets an area of 176 lines Setting A-2 Register Scroll area start line register (R22) Scroll area line count register (R24) Setting Value 00H 57H Details of Setting Value Sets Y address 00H Sets an area of 88 lines Setting A-3 Register Scroll area start line register (R22) Scroll area line count register (R24) Setting Value 58H 57H Details of Setting Value Sets Y address 58H Sets an area of 88 lines Setting A-4 Register Scroll area start line register (R22) Scroll area line count register (R24) Setting Value 2CH 57H Details of Setting Value Sets Y address 2CH Sets an area of 88 lines 34 Preliminary Product Information S14797EJ3V7PM PD161620 Figure 5-17. Display Scroll Setting Examples Setting A-1 144 Gate 1 Source Gate 1 1 Source 1 Setting A-2 144 Scroll area Scroll area 88 89 Fixed display area 176 176 Source Gate 1 1 Setting A-3 144 Gate Source 1 1 Setting A-4 144 Fixed display area 44 45 Fixed display area 88 89 Scroll area Scroll area 132 133 Fixed display area 176 176 Preliminary Product Information S14797EJ3V7PM 35 PD161620 (3) Scroll setting flowchart example Start IR Scroll area start line register assignment R22 Scroll area start line register setting IR Scroll area line count register assignment R24 Scroll area line count register setting IR Scroll step count register assignment R26 Scroll step count register setting (1 step) IR X address register assignment R3 X address register setting IR Y address register assignment R5 Y address register setting D7 to D0 Y address register RS MSB LSB D5 to D0 Index register RS MSB LSB L X X 0 1 0 1 1 0 D7 to D0 Scroll area start line register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are the data for Scroll area start line. D5 to D0 Index register RS MSB LSB L X X 0 1 1 0 0 0 D7 to D0 Scroll area line count register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are the data for Scroll area line count register. D5 to D0 Index register RS MSB LSB L X X 0 1 1 0 1 0 D7 to D0 Scroll step count register RS MSB LSB H 0 0 0 0 0 0 0 1 D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 1 1 D7 to D0 X address register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 depend on application condition. D5 to D0 Index register RS MSB LSB L X X 0 0 0 1 0 0 H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 depend on application condition. 36 Preliminary Product Information S14797EJ3V7PM PD161620 IR Display memory assignment Display data Re-write scrolling area 1 (Start) Display data Re-write scrolling area 2 Display data Re-write scrolling area n (End) IR Scroll step count register assignment R26 Scroll step count register setting (2 steps) IR X address register assignment R3 X address register setting IR Y address register assignment R50 Y address register setting IR Display memory assignment R11 R11 R11 D5 to D0 Index register RS MSB LSB L X X 0 0 1 0 1 1 D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are display memory data. D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are display memory data. D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D1 are display memory data. D5 to D0 Index register RS MSB LSB L X X 0 1 1 0 1 0 D7 to D0 Scroll step count register RS MSB LSB H 0 0 0 0 0 0 1 0 D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 1 1 D6 to D0 X address register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 depend on application condition. D5 to D0 Index register RS MSB LSB L X X 0 0 0 1 0 0 D7 to D0 Y address register RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D1 depend on application condition. D5 to D0 Index register RS MSB LSB L X X 0 0 1 0 1 1 Preliminary Product Information S14797EJ3V7PM 37 PD161620 Display data Re-write scrolling area 1 (Start) R11 D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are display memory data. R11 D7 to D0 Display memory RS MSB LSB Display data Re-write scrolling area 2 Display data Re-write scrolling area n (End) Next transaction R11 H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are display memory data. D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0 are display memory data. (Repeat) 38 Preliminary Product Information S14797EJ3V7PM PD161620 (4)Scroll function example Scroll area start line register (R22): 2CH Scroll area line count register (R24): 58H (a)Scroll step count register setting (R26): 00H Source Gate 1 1 Fixed display area 44 45 2BH 2CH 144 Y address 00H Scroll area 132 133 Fixed display area 176 83H 84H AFH (b)Scroll step count register setting (R26): 01H Source Gate 1 1 Fixed display area 44 45 2BH 2DH 144 Y address 00H Scroll area 132 133 Fixed display area 176 83H 2CH 84H AFH Preliminary Product Information S14797EJ3V7PM 39 PD161620 (c)Scroll step count register setting (R26): 02H Source Gate 1 1 Fixed display area 44 45 2BH 2EH 144 Y address 00H Scroll area 132 133 Fixed display area 176 83H 2CH 2DH 84H AFH (d)Scroll step count register setting (R26): 57H Source Gate 1 1 Fixed display area 44 45 2BH 83H 2CH 144 Y address 00H Scroll area 132 133 Fixed display area 176 82H 84H AFH 40 Preliminary Product Information S14797EJ3V7PM PD161620 5 5.11 Initialization Setting Sequence Example Power ON hard reset (/RESET = L) IR Reset register assignment R2 Reset register setting RS MSB LSB D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 1 0 D7 to D0 Reset RS MSB LSB H X X X X X X X 1 D5 to D0 Index register RS MSB LSB L X X 1 0 0 0 0 0 D7 to D0 Power supply control register 1 RS MSB LSB H X D6 D5 D4 D3 0 0 0 Note D6 to D4 depend on application condition., D3 to D0:gate driver, power supply IC regulator OFF, DC/DC converter OFF D5 to D0 Index register RS MSB LSB L X X 1 0 0 0 1 0 D7 to D0 Power supply control register2 RS MSB LSB H X X X X D3 D2 X X Note D3, D2 depend on application condition. D5 to D0 Index register RS MSB LSB L X X 1 0 0 0 0 0 H X D6 D5 D4 D3 1 1 1 Note D6 to D4 depend on application condition., D3 to D0:gate driver, power supply IC regulator OFF, DC/DC converter OFF Preliminary Product Information S14797EJ3V7PM 41 PD161620 IR Control register 1 assignment R0 Control register 1 setting IR Control register 2 assignment R1 Control register 2 setting IR Invert set register assignment R6 Invert set register setting IR Calibration register assignment R38 Calibration register setting (calibration start) IR Calibration register assignment R38 Calibration register setting (calibration stop) D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 0 0 D7 to D0 Control register1 RS MSB LSB H 0 0 0 X X D2 Note D7: Normal write mode D6: Display OFF D5: Standby OFF D2 and D1: depend on application condition Always write to 0 in D0 D5 to D0 Index register RS MSB D1 0 LSB L X X 0 0 0 0 0 1 D7 to D0 Control register 2 RS MSB LSB H 0 0 D5 0 0 0 0 D0 Note D7: All data 0 display OFF (normal mode) D4: Normal driving mode D2: 4096-color mode D1: Normal display mode D5 and D0: depend on application condition Always write to 0 in both D6 and D3 D5 to D0 Index register RS MSB LSB L X X 0 0 0 1 1 0 D7 to D0 Invert set register RS MSB LSB H X X X X X Note D0 depends on application condition. D5 to D0 Index register RS MSB X X D0 LSB L X X 1 0 0 1 1 0 D7 to D0 Calibration register RS MSB LSB H X X X X X Note Calibration wait time (tcal) tcal = 1/(frame frequency x 177) D5 to D0 Index register RS MSB X X 1 LSB L X X 1 0 0 1 1 0 D7 to D0 Calibration register RS MSB LSB H X X X X X X X 0 42 Preliminary Product Information S14797EJ3V7PM PD161620 IR X address register assignment R3 X address register setting IR Y address register assignment R5 Y address register setting IR Display memory assignment Display data write 1 (start) R11 Display data write 2 Display data write n (end) R11 R11 D7 to D0 Display memory RS MSB LSB D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 1 1 D7 to D0 X address register RS MSB LSB H 0 0 0 0 0 0 0 0 X address: 00H D5 to D0 Index register RS MSB LSB L X X 0 0 0 1 0 1 D7 to D0 Y address register RS MSB LSB H 0 0 0 0 0 0 0 0 Y address: 00H D5 to D0 Index register RS MSB LSB L X X 0 0 1 0 1 1 H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0: display memory data D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0: display memory data D7 to D0 Display memory RS MSB LSB H D7 D6 D5 D4 D3 D2 D1 D0 Note D7 to D0: display memory data Preliminary Product Information S14797EJ3V7PM 43 PD161620 IR Control register 1 assignment R0 Control register 1 setting Nest transaction D5 to D0 Index register RS MSB LSB L X X 0 0 0 0 0 0 D7 to D0 Control register 1 RS MSB LSB H 0 1 0 X X D2 D1 0 Note D7: Normal write mode D6: Display ON D5: Standby OFF D2 and D1: depend on application condition Always write to 0 in D0 44 Preliminary Product Information S14797EJ3V7PM PD161620 6. RESET If the /RESET input becomes L or the reset command is input, the internal timing generator is initialized. The reset command will also initialize each register to its default value. These default values are listed in the table below. Register Index register Control register 1 Control register 2 IR R0 R1 R3 R5 R6 R11 R22 R24 R26 R27 R28 R29 R30 R31 R32 R34 R38 R42 R43 R44 to R47 /RESET Pin Note 1 X X X X X X X X X X X X X X X X X X X X X Reset Command O O O O O O X O O O O O O O O O O O O O O Default Value 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 01H 00H 00H 00H 5 X address register Y address register Reverse setting register Display memory Note 2 Scroll area start line register Scroll area line count register Scroll step count register Partial off area color register Partial 1 display area start line register Partial 2 display area start line register Partial 1 display area line count register Partial 2 display area line count register Power supply control register 1 Power supply control register 2 Calibration register Output port register Input port register Note 3 5 Test mode O: Default value set, X: Default value not set Notes 1. The internal counters are initialized only by a reset from the /RESET pin. Be sure to perform reset via the /RESET pin at power application. 2. The contents of RAM are saved in the case of both reset by /RESET pin and reset by reset command. Note that the RAM contents are T.B.D. immediately after the power is turned on. 3. The following value is set as the calibration setting time, tcal, in a reset by reset command. tcal = 1/fOSC x 32 5 Remark T.B.D. (to be determined.) Preliminary Product Information S14797EJ3V7PM 45 PD161620 7. COMMAND 5 7.1 Command List Index Register 5 1st byte 2nd byte Register Name 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R/W 7 6 5 Data Bits 4 3 IR3 2 IR2 ADX 1 0 IR0 IR1 ADC COLOR DTY XA2 YA2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Index register Control register 1 Control register 2 Reset X address register Y address register Reverse setting register W IR5 IR4 R/W RMW DISP STBY R/W FDM DTX LPM W R/W XA7 XA6 XA5 XA4 R/W R/W YA7 YA6 YA5 YA4 XA3 YA3 INC CRES XA1 XA0 YA0 INV YA1 Display memory R/W D7 D6 D5 D4 D3 D2 D1 D0 Scroll area start line register Scroll area line count register Scroll step count register Partial off area color register Partial 1 display area start line register Partial 2 display area start line register Partial 1 display area line count register Partial 2 display area line count register Power supply control register 1 Power supply control register 2 R/W SSL7 SSL6 SSL5 SSL4 SSL3 SSL2 SSL1 SSL0 R/W SAW7 SAW6 SAW5 SAW4 SAW3 SAW2 SAW1 SAW0 R/W SST7 SST6 SST5 SST4 SST3 SST2 SST1 SST0 PGD2 PGD1 PGD0 R/W R/W P1SL7 P1SL6 P1SL5 P1SL4 P1SL3 P1SL2 P1SL1 P1SL0 R/W P2SL7 P2SL6 P2SL5 P2SL4 P2SL3 P2SL2 P2SL1 P2SL0 R/W P1AW7 P1AW6 P1AW5 P1AW4 P1AW3 P1AW2 P1AW1 P1AW0 R/W P2AW7 P2AW6 P2AW5 P2AW4 P2AW3 P2AW2 P2AW1 P2AW0 BGRS VCE VCD2 PVCOM RGONG RGONP DCON R/W R/W VCD12 VCD11 Calibration register R/W OC Output port register Input port register Test mode Test mode Test mode Test mode W R R/W R/W R/W R/W OP3 IP3 OP2 IP2 OP1 IP1 OP0 IP0 Remark : These registers cannot be used. Cautions 1. If a write-only register is read, invalid data will be output. 5 Also, the RS signal during the write operation becomes invalid. 2. A low level is output when an unused register is read. 46 Preliminary Product Information S14797EJ3V7PM PD161620 7.2 Command Explanation (1/4) Resistor Bit D7 Symbol RMW Function This bit enables/disables use of the read-modify-write mode function. Perform read/write switching in the read-modify-write mode at every 2-byte access in the 1-pixel/2-byte mode. Similarly, in the 2-ixel/3-byte mode, perform read/write switching at every 3-byte access 0: Address is incremented by one each time a display data read or write 1: Read modify write mode (address is incremented by one each time a display data write only) D6 DISP This bit switches display ON/OFF. When display OFF is selected, output is performed as when all the data is "1", regardless of the internal RAM data. (In the case of normally white, white display is performed.) This command is executed from the time the next line data is output. 0: Display off (All output pins are VSS level, OSC and DC/DC converter are working) 1: Display on D5 STBY This bit selects the standby function. When the standby function is selected, a display OFF operation is executed and the amplifiers at each output stage and the operation of internal oscillation circuit are stopped. However, standby control cannot be performed for the gate IC ( PD161640) connected to 5 R0 PD161620 and the power supply IC ( PD161660). Therefore, after executing the standby function using this bit, set both the regulator for the gate IC and power supply IC to off and set the DC/DC converter to OFF. For the sequence, refer to the preliminary product information machine of the PD161660. Note that when releasing standby, perform the opposite operation, i.e., after setting the DC/DC converter to ON and setting the regulators of the gate IC and power supply IC to ON, execute the normal operation command. 0: Normal operation 1: Stand-by function (Display read off from RAM, stop both OSC and VCOM, display off = entire data is output as 1 ) D2 D1 ADX ADC FDM Switches X address addressing X address direction Column address direction This bit does not depend on the internal RAM data. This function performs output in the same way as when all the data is "0". (In the case of normally white, black display is performed.) This command is executed from the time the next line data is output. 0: Normal operation 1: RAM data is ignored and the entire data is output as 0. D5 DTX This bit selects the method for transferring data to internal RAM. 0: 2-pixel / 3-byte 1: 1-pixel / 2-byte D4 LPM This bit is used when setting the gate IC ( PD161640) and power supply IC ( PD161660) to the lowpower mode. When the low-power mode is selected, the LPMG pin and the LPMP pin signals change from low to high (output changes immediately following command execution.). The LPMG pin must be connected to the LPM pin of the gate IC, and the LPMP pin must be connected to the LPM pin of the power supply IC. 0: Normal 1: Low power mode 5 R1 D7 Preliminary Product Information S14797EJ3V7PM 47 PD161620 (2/4) Resistor D2 Bit Symbol COLOR Function This pin switches the 4096-color mode and the 8-color mode. When the 8-color mode is selected, low power supply can be selected in order to stop the amplifier at each output stage. In the 8-color mode, the value of the MSB of the internal RAM data is used as the color data. This command is executed following transfer from the time the next line data is output. 0: 4096-color mode (12 bits/pixels) 1: 8-color mode (3 bits/pixels) D1 DTY This pin selects the partial function. When the partial function s selected in the 4096-color mode, set the partial-OFF area-color selection register (R27) to 00H. In the 8-color mode, the partial OFF area color can be set to any value from 00H to 07 H. The power consumption cannot be reduced with the partial function. To reduce the power consumption, select the 8-color mode. This command is executed following transfer from the time the next line data is output. 0: Normal display mode 1: Partial display mode D0 INC This pin selects the address increment direction. In the case of the 8-bit parallel interface mode and the serial interface mode, when Y address increment is selected, only the 1-pixel/2-byte mode can be selected as the data transfer mode. However, when X address increment is selected, both the 1-pixel/2-byte and 2-pixel/3-byte modes can be selected. 0: X address increment 1: Y address increment 5 R2 D0 CRES Command reset function. Be sure to execute this bit after power ON. Command reset automatically clears this bit following execution (CRES = 01H). Therefore, it is not necessary to set 0 (select normal operation) again by software. Moreover, since the time required for the value of this bit to change (1 0) following command reset execution is extremely short, it is not necessary to secure time until the next command is set following command reset setting. 0: Normal operation 1: Command reset 5 5 5 R3 R5 R6 D7 to D0 D7 to D0 D0 XA7 to XA0 YAn INV This register sets the X address. Set a value between 00H and 8FH. This register sets the Y address. Set a value between 00H and 8FH. This bit selects between the line inversion function and the frame inversion function. The mode selected by this command is executed from the start of the next scan after the gate scan in progress when this command was executed has completed 176 lines. When the reset command is input, the INV register is initialized. 0: Line inversion with same line. 0: Line inversion 1: Frame inversion 5 R11 R22 R24 R26 D7 to D0 D7 to D0 D7 to D0 D7 to D0 Dn SSLn SAWn SSTn These bits are used for reading/writing data from /to display memory (internal RAM). Scroll area start line register (00H to AFH) Scroll area line count register (00H to AFH) Scroll step count register (00H to AFH), invalid in partial display mode 48 Preliminary Product Information S14797EJ3V7PM PD161620 (3/4) Resistor Bit D2 to D0 Symbol PGDn Function Partial off area color register (000H to 111H) The relationship between each color data and the bits of this register is as follows. This relationship does not depend on the ADX and ADC values D11 to D8: PGD0 D7 to D4: PGD1 D3 to D0: PGD2 R28 R29 D7 to D0 D7 to D0 D7 to D0 P1SLn P2SLn P1AWn Partial1 display area start line register (00H to AFH) Partial2 display area start line register (00H to AFH) Partial1 display area line count register (00H to AFH) When this register is 0, the values of the partial 2 display area start line register (R29) and the partial 2 display area line count register (R31) are not valid. R31 D7 to D0 D6 P2AWn BGRS Partial2 display area line count register (00H to AFH) This pin selects whether to use the internal power supply or an external power supply (input from the BRGIN pin) for generation the common center voltage output from the VCOM pin. 0: The internal power-supply is selected as the VCOM power supply 1: Input from the external power-supply BGRIN is selected as the BCOM power supply D5 VCE Selects the VO output level of the power supply IC ( PD161660). The VCE pin of this IC and the VCE pin of the power supply IC must be connected. 0: The Vo high-level booster voltage level is VDD1 minus 1 level 1: The Vo high-level booster voltage level is the same level as VDD1 D4 VCD2 Selects the VDD2 output level of the power supply IC ( PD161660). The VCD2 pin of this IC and the VCD2 pin of the power supply IC must be connected. 0: VDD2 = VDC x 2 1: VDD2 = VDC x 3 D2 RGONG Switches the internal regulator of the gate IC ( PD161640) ON/OFF. When OFF is selected, a low level is output from the RGONG pin, and when ON is selected, a high level is output from the RGONG pin. The RGONG pin of this IC and the RGON pin of the gate IC must be connected. 0: Regulators of gate driver (VB) are off 1: Regulators of gate driver (VB) are on D1 RGONP Switches the internal DC/DC converter of the power supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the RGONP pin, and when ON is selected, a high level is output from the RGONP pin. The RGONP pin of this IC and the RGON pin of the power supply IC must be connected. 0: Regulators of power supply IC (VT, VS) are off 1: Regulators of power supply IC (VT, VS) are on D0 DCON Switches the internal DC/DC converter of the power supply IC ( PD161660) ON/OFF. When OFF is selected, a low level is output from the DCON pin, and when ON is selected, a high level is output from the DCON pin. The DCON pin of this IC and the DCON pin of the power supply IC must be connected. 0: DC/DC converter is off 1: DC/DC converter is on 5 R27 5 R30 5 R32 Preliminary Product Information S14797EJ3V7PM 49 PD161620 (4/4) Resistor Bit D3, D2 Symbol VCD12, VCD11 Function Performs booster control for the DC/DC converter in the power supply IC ( PD161660) The data set with this bit is output from the VCD11 pin and the VCD12 pin. The VCD11 pin and VCD12 pin of PD161620 must be connected to the VCD11 pin and the VCD12 pin of the power supply IC. VCD12, VCD11 = 0, 0: VDD1 = VDC x 4 = 0, 1: VDD1 = VDC x 5 = 1, 0: VDD1 = VDC x 6 = 1, 1: VDD1 = VDC x 7 5 R34 5 R38 D0 OC This bit is used for calibration. The time from calibration start command execution until calibration stop command execution becomes the time for 1 line. 0: Calibration start 1: Calibration stop 5 R42 D3 to D0 OPn Output port (OP3 to OP0) write When after the R42 register is specified in the index register, writing to the R42 register is performed, the values written to the OP3 to OP0 pins are output. 5 R43 D3 to D0 IPn Input port (IP3 to IP0) read To read the IP3 to IP0 inputs, use the following method. R44 R45 R46 R47 - - Test mode (for IC testing only) 50 Preliminary Product Information S14797EJ3V7PM PD161620 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25C, VSS = 0 V) Parameter Power supply voltage Power supply voltage Power supply voltage Power supply voltage for -curve correction Input voltage Input current Operating ambient temperature Storage temperature VS VCC1 VCC2 V1 to V15 VI II TA Tstg Symbol Ratings -0.5 to +6.5 -0.5 to +6.5 -0.5 to VCC1 + 0.5 -0.5 to VS + 0.5 -0.5 to VCC1 + 0.5 10 -40 to +85 -55 to +125 Unit V V V V V mA C C 5 Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions (TA = -40 to +85C, VSS = 0 V) Parameter Symbol VS VCC1 VCC2 VI Note1 VI Note2 MIN. 3.6 2.5 1.8 0 0 TYP. 4.0/5.0 2.7 MAX. 5.5 3.6 VCC1 VCC1 VCC2 Unit V V V V V 5 Power supply voltage 5 5 Input voltage Notes 1. Pins of VCC1 power-supply system: PSX0, PSX1, OSEL, C86, TESTOUT, IP0 to IP3, OP0 to OP3, LPMG, LPMP, GOE1, GOE2, GSTB, GCLK, DCON, RGONP, RGONG, VCD11, VCD12, VCD2, VCE, OSCSEL, TESTIN 5 2. Pins of VCC2 power-supply system: /CS1, CS2, /RD(E), /WR(R,/W), RDY, D0 to D4, D5(SO), D6(SCL), D7(SI), RS, /RESET, GSB, OSCIN Preliminary Product Information S14797EJ3V7PM 51 PD161620 5 Electrical Specifications (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 V to VCC1, VS = 3.6 to 5.5 V) Parameter Symbol VCC1 VCC2 VCC1 VCC2 VCC1, IOUT = -100 A VCC2, IOUT = -1 mA VCOUT, IOUT = -100 A VCC1, IOUT = 100 A VCC2, IOUT = 1 mA VCOUT, IOUT = 100 A ISOURCE = 40 A ISINK = -40 A D0 to D7, TESTIN TESTIN Except D0 to D7 D0 to D7 D0 to D7 VX = 3.0 V, VOUT = 4.0 V, VS = 5.0 V 20 60 VCOM - 12.5 VCOM + 12.5 1 130 -1 10 -10 -100 0.9 VCC1 0.8 VCC2 0.9 VS 0.1 VCC1 0.2 VCC2 0.1 VS Condition MIN. High level input voltage VIH1 VIH2 Low level input voltage VIL1 VIL2 High level output voltage VOH1 VOH2 VOH3 Low level output voltage VOL1 VOL2 VOL3 VCOM output voltage VCOMH VCOML 0.8 VCC1 0.8 VCC2 0.2 VCC1 0.2 VCC2 Specification TYP.Note MAX. V V V V V V V V V V mV mV Unit 5 High level input current Low level input current High level leakage current Low level leakage current IIH1 IIH2 IIL1 ILIH ILIL IVOH A A A A A A A 5 High level driver output current 5 Low level driver output current 5 Driver output deviation 5 Internal reference voltage variation for VCOM output IVOL VO VCOM VX = 2.0 V, VOUT = 1.0 V, VS = 5.0 V 150 30 -6 0 6 mV V 5 Current consumption ICC1 ICC2 IS VCC1 (when non-access CPU) VCC2 (when non-access CPU) 4096-color mode 8-color mode Stand-by mode 90 135 1 A A A A A 800 100 1200 150 5 Note TYP. values are reference values when TA = 25C 52 Preliminary Product Information S14797EJ3V7PM PD161620 5 AC Characteristics (Unless Otherwise Specified, TA = -40 to +85C, VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 V to VCC1, VS = 3.6 to 5.5 V) (a) i80 series CPU interface RS tAS8 /CS1 (CS2 = 1) tCYC8 tCCLW, tCCLR tf tr tAH8 /WR, /RD tCCHR, tCCHW tDS8 D0 to D7 (Write) tACC8 D0 to D7 (Read) tOH8 tDH8 Preliminary Product Information S14797EJ3V7PM 53 PD161620 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter Address hold time Address setup time System cycle time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF 10 Condition RS RS MIN. 0 0 250 120 140 60 80 80 5 140 140 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns 5 5 5 5 5 5 5 Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 2.5 V, VCC1 VCC2 Parameter Address hold time Address setup time System cycle time Symbol tAH8 tAS8 tCYC8 tCCLW tCCLR tCCHW tCCHR tDS8 tDH8 tACC8 tOH8 /WR /RD /WR /RD D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF 10 Condition RS RS MIN. 0 0 333 120 160 100 140 100 5 180 180 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns 5 5 5 5 5 5 Control low-level pulse width (/WR) Control low-level pulse width (/RD) Control high-level pulse width (/WR) Control high-level pulse width (/RD) Data setup time Data hold time /RD access time Output disable time Note TYP. values are reference values when TA = 25C. Remarks 1. The input signal's rise/fall times (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. 54 Preliminary Product Information S14797EJ3V7PM PD161620 (b) M68 series CPU interface RS R,/W tAS6 /CS1 (CS2 = 1) tCYC6 tEWHR, tEWHW tf tr tAH6 E tEWLR, tEWLW tDS6 D0 to D7 (Write) tACC6 D0 to D7 (Read) tOH6 tDH6 Preliminary Product Information S14797EJ3V7PM 55 PD161620 When VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter Address hold time Address setup time System cycle time Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 Read Write Read Write tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF E E E E 10 140 120 80 60 Condition RS RS MIN. 0 0 250 80 0 110 100 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns 5 Data setup time Data hold time Access time Output disable time 5 Enable high pulse width 5 Enable low pulse width Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. When VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 2.5 V, VCC1 VCC2 Parameter Address hold time Address setup time System cycle time Data setup time Data hold time Access time Output disable time Symbol tAH6 tAS6 tCYC6 tDS6 tDH6 tACC6 tOH6 Read Write Read Write tEWHR tEWHW tEWLR tEWLW D0 to D7 D0 to D7 D0 to D7, CL = 100 pF D0 to D7, CL = 100 pF E E E E 10 160 120 140 100 Condition RS RS MIN. 0 0 333 100 0 150 150 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns ns ns 5 Enable high pulse width 5 Enable low pulse width Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. When using a fast system cycle time, the rated value range is either (tr + tf) < (tCYC6-tEWLR-tEWHR) or (tr + tf) < (tCYC6-tEWLW-tEWHW). 2. All timing is rated based on 20 to 80% of VCC2. 56 Preliminary Product Information S14797EJ3V7PM PD161620 (c) RDY timing Write cycle (Display data write) /CS1 (CS2 = 1) tRDWE /WR (i80) E (M68) tRYR1 tWP tRYZ tRYF tRYR2 tDS8/tDS6 tDH8/tDH6 5 RDY 5 D0 to D7 (Write) VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 VCC2 Parameter RDY output delay time (CS) RDY output delay time (/WR, E) Symbol tRYR1 tRYR2 tRYF tWP tRDWE tRYZ tDS8/6 tDH8/6 Note 2 100 0 Condition CL = 15 pF CL = 15 pF Note 1 Note 1 0 1000 90 MIN. TYP. MAX. 110 160 850 Unit ns ns ns ns ns ns ns ns 5 RDY low level time Write pulse width RDY to /WR, E time RDY output delay time 5 Data setup time Data hold time Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Notes 1. VCC2 1.8 k 1.0 k 60 pF 2. VCC2 1.8 k 1.0 k 5 pF Preliminary Product Information S14797EJ3V7PM 57 PD161620 Write cycle (Display data read) /CS1 (CS2 = 1) tRDRE /RD (i80) /E (M68) tRYR1 tRP tRYZ tRYR2 tRYF 5 RDY D0 to D7 (Read) tACC8/tACC6 tOH8/tOH6 VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 VCC2 Parameter RDY output delay time (CS) Symbol tRYR1 tRYR2 tRYF2 tRP tRDRE tRYZ tACC8/6 tOH8/6 Note 2 CL = 100 pF CL = 100 pF 10 Condition CL = 15 pF CL = 15 pF Note 1 Note 1 0 1000 90 150 150 MIN. TYP. MAX. 110 160 850 Unit ns ns ns ns ns ns ns ns 5 5 RDY output delay time (/RD, E) RDY low level time Read pulse width RDY to /WR, E time RDY output delay time 5 5 Read data access time Data hold time Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Notes 1. VCC2 1.8 k 1.0 k 60 pF 2. VCC2 1.8 k 1.0 k 5 pF 58 Preliminary Product Information S14797EJ3V7PM PD161620 Write cycle (Display data write) /CS1 (CS2 = 1) tRDWE /WR (i80) E (M68) tRYR1 tWP tRYZ tRYF tRYR2 tDS8/tDS6 tDH8/tDH6 5 RDY 5 D0 to D7 (Write) VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter RDY output delay time (CS) RDY output delay time (/WR, E) Symbol tRYR1 tRYR2 tRYF2 tWP tRDWE tRYZ tDS8/6 tDH8/6 Note 2 80 0 Condition CL = 15 pF CL = 15 pF Note 1 Note 1 0 1000 70 MIN. TYP. MAX. 80 140 850 Unit ns ns ns ns ns ns ns ns 5 RDY low level time Write pulse width RDY to /WR, E time RDY output delay time 5 Data setup time Data hold time Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Notes 1. VCC2 1.8 k 1.0 k 60 pF 2. VCC2 1.8 k 1.0 k 5 pF Preliminary Product Information S14797EJ3V7PM 59 PD161620 Read cycle (Display data read) /CS1 (CS2 = 1) tRDRE /RD (i80) tRP /E (M68) tRYR1 tRYZ tRYR2 tRYF 5 RDY D0 to D7 (Read) tACC8/tACC6 tOH8/tOH6 VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter RDY output delay time (CS) RDY output delay time (/RD, E) Symbol tRYR1 tRYR2 tRYF2 tRP tRDRE tRYZ tACC8/6 tOH8/6 Note 2 CL = 100 pF CL = 100 pF 10 Condition CL = 15 pF CL = 15 pF Note 1 Note 1 0 1000 70 110 100 MIN. TYP. MAX. 80 140 850 Unit ns ns ns ns ns ns ns ns 5 RDY low level time Read pulse width RDY to /RD, E RDY output delay time Read data access time Data hold time Remarks 1. The rise and fall times (tr and tf) of input signals are rated at 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Notes 1. VCC2 1.8 k 1.0 k 60 pF 2. VCC2 1.8 k 1.0 k 5 pF 60 Preliminary Product Information S14797EJ3V7PM PD161620 (d) Serial interface tCSS /CS1 (CS2 = 1) tSAS RS tSCYC tSLW SCL tf tSDS SI tr tSHW tSAH tCSH tSDH VCC1 = 2.5 to 3.6 V, VCC2 = 1.8 to 1.9 V, VCC1 VCC2 Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI /CS1, CS2 /CS1, CS2 Condition MIN. 250 100 100 150 150 100 100 150 150 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. VCC1 = 2.5 to 3.6 V, VCC2 = 2.5 to 3.6 V, VCC1 VCC2 Parameter Serial clock cycle SCL high-level pulse width SCL low-level pulse width Address hold time Address setup time Data setup time Data hold time CS - SCL time Symbol tSCYC tSHW tSLW tSAH tSAS tSDS tSDH tCSS tCSH SCL SCL SCL RS RS SI SI /CS1, CS2 /CS1, CS2 Condition MIN. 150 60 60 90 90 60 60 90 90 TYP. Note MAX. Unit ns ns ns ns ns ns ns ns ns Note TYP. values are reference values when TA = 25C. Remarks 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less. 2. All timing is rated based on 20 to 80% of VCC2. Preliminary Product Information S14797EJ3V7PM 61 PD161620 (e) Common Parameter Oscillation frequency Symbol fOSC tcal (fFRAME0) fFRAME1 fFRAME2 fFRAME3 Input oscillation frequency Reset pulse width at power on Reset pulse width Reset time fOSCIN tVR tRW tR /RESET to interface operation Uncalibrated Calibrated Note 3 Calibrated Note 4 External oscillator VCC1 or VCC2 to /RESET Condition Internal oscillator Note 2 MIN. 260 47 (120) 46 76 79 260 100 100 100 TYP.Note 1 412 77.6 (72.8) 73 80 80 MAX. 680 93 (60.7) 120 84 81 680 Unit kHz 5 5 Calibration setting time (frame frequency) Frame frequency s (Hz) Hz Hz Hz kHz ns ns ns Notes 1. TYP. values are reference values when TA = 25C. 2. The relationship between the frame frequency and the calibration setting time is as follows (n: line count). 5 fFRAME0 = 1 tcal x 177 3. Measured at TA = -40 to +85C, after calibration at frame frequency = 80 Hz, TA = 25C exactly. 4. Measured at 5C, after calibration at frame frequency = 80 Hz exactly. 62 Preliminary Product Information S14797EJ3V7PM PD161620 5 9. CONNECTION of PD161620, 161640, and 161660 The connection of the PD161620, 161640, and 161660 is outlined below. 1.7 V to VCC1 CPU An /CS1, CS2 /RD(E) /WR(R,/W) D7 to D0 RESET VDD VCOMR VCOM VCOMOUT WAIT RDY VSS 2.5 V to 3.6 V RS /CS1, CS2 /RD(E) /WR(R,/W) D7 to D0 RESET VCC1 VCC1 VCC2 VS DCON VS 2.5 V to 5.5 V VDC DCON RGONP VCE VCD11 VCD12 VCCD22 LPM RGONP VCE VCD11 VCD12 VCCD22 LPMP uPD161660 VSS UPD161620 VT VO GND(0 V) GCLK GSTB GOE1 GOE2 RGONG GSB Y432 Y431 LPMP COMMON Y2 Y1 O1 O2 VCC1 VEE VT CLK STVR(STVL) OE1 OE2 RGONG SB LPM TFT-LCD Panel O176 uPD161640 VSS Preliminary Product Information S14797EJ3V7PM 63 PD161620 5 The appearance of the PD161620, 161640, and 161660 when they are connected face-up is as follows. Sample UPD161620/40/60 connection diagram Capacitor and diode connected to power supply IC VDD1: 1 uF, 25 V withstandiing voltage, VDD2: 1 uF, 10 V withstanding voltage, VT, VREF: 0.1 uF, 10 V withstanding voltage, VDC: 1 uF, 10 V withstanding voltage, VCC1: 1 uF, 10 V withstanding voltage VCC1 vss DUMMY VCD12 VCD2 VCE DUMMY DUMMY VDC DUMMY DUMMY VS MVS VREF VT MVT VDD1 VDD2 DUMMY Diode: 40 V withstanding voltage 1 uF, 25 V withstanding voltage 1 uF 4.7 to 10 uF, 10 V withstanding voltage Variable resistor: 51 to 100 k Variable resistor: 51 to 150 k Resistor Resis Resisto 200 k 0.1 to 10 uF, 10 V withstanding voltage CPU I/F Y1 Y2 Y3 Y5 Y4 Y3 Y2 Y1 DUMMY TEST7 TEST8 TEST9 TEST1 DVSS TEST2 DVCC1 TEST3 DVSS TEST4 TEST5 DVCC1 OSCSEL DVSS C86 DVCC1 PSX0 DVSS PSX1 DVCC1 DVSS OSCIN RDY /RESET /CS1 D7(SI) D6(SCL) D5(SO) D4 D3 D2 D1 D0 RS /WR(R,/W) /RD(E) SSB CS2 VCC2 TESTIN TESTOUT VCE VCD2 VCD12 VCD11 LPMP RGONP DCON VCOUT VCOM DUMMY DUMMY DUMMY VCC1 VSS VS VCOMR BGRIN DVSS DVCC1 TEST6 VRH V0 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 VRL1 VRL2 OP0 OP1 OP2 OP3 DVSS IP0 IP1 IP2 IP3 DVCC1 GSTB GCLK GOE1 GOE2 RGONG LPMG TEST10 Face Up To COM DUMMY LACS0 VSS TESTIN6 TESTOUT TESTIN5 TESTIN4 DUMMY DUMMY VCC1 DUMMY VSS DUMMY TESTIN3 TESTIN2 TESTIN1 DUMMY DUMMY VCD11 LPM RGONP DCON EXRVT EXRVS LFS1 LFS0 FS1 FS0 RSEL ACS1 ACS0 VREFSEL LACS1 DAMMY Face Up DUMMY VO C6+ C6C5+ C5C4+ C4C3+ C3C2+ C2C1+ C1DUMMY DUMMY DUMMY Diode: 40 V withstanding voltage C1 to C6: 1 uF, 10 V withstanding voltage O176 O175 O174 O3 O2 O1 TEST1 TEST2 PVCC1 LACS0 PVSS LACS1 PVCC1 ACS0 PVSS ACS1 PVCC1 R,/L PVSS EXRV PVCC1 RSEL PVSS OSEL PVCC1 VREF VR VB VT VEE VSS VCC1 VB VR MVR STVR STVL CLK OE1 OE2 RGONG LPM SB 64 Preliminary Product Information S14797EJ3V7PM Face Up PD161620 5 10. EXAMPLE of PD161620 and CPU CONNECTION Examples of PD161620 and CPU connection are shown below. In parallel interface mode, connect the RDY signal to the external WAIT pin of the CPU to execute wait control. In the example below, RS pin control in parallel interface mode is described for the case when the least significant bit of the address bus is being used. (1) i80 series format CPU VDD VSS /CS A0 D0 to D7 /RD /WR /WAIT /RESET PD161620 (2) M68 series format CPU VDD VSS /CS A0 D0 to D7 R,/W E /WAIT /RESET PD161620 VCC2 VSS /CS1 RS D0 to D7 /RD /WR RDY /RESET VCC2 VSS /CS1 RS D0 to D7 R,/W E RDY /RESET (3) Serial interface CPU VDD VSS /CS PORT SCL SI SO /RESET PD161620 VCC2 VSS /CS1 RS SCL SO SI /RESET Preliminary Product Information S14797EJ3V7PM 65 PD161620 11. REVISION HISTORY (1/2) Edition/ Date This edition 1st edition/ S14797EJ1V0PM00 Apr. 2000 2nd edition/ S14797EJ2V0PM00 Aug. 2000 - Page Previous edition - Type of revision - - Description Location Throughout Throughout Throughout p.2 p.7 p.10 p.12 p.12 p.12 p.14 p.14 p.15 p.16 p.17 p.18 p.19 p.19 p.22 p.27 p.36 p.37 p.46 p.50 Throughout Throughout Throughout p.2 p.7 p.10 p.11 p.11 p.11 p.13 p.13 - p.14 p.15 - p.17 - - - p.19 p.20 - p.28 Modification Modification Modification Modification Modification Modification Modification Modification Addition Addition Modification Addition Addition Addition Modification Modification Addition Addition Addition Modification Modification Addition Modification Title R22 register name R24 register name 1. BLOCK DIAGRAM 3. PIN FUNCTIONS 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS 5.1 title 5.1.1 Selection of interface type 5.1.2 Selection of data transfer mode Figure 5-3 Figure 5-4 title 5.1.4 Serial interface 5.2.1 X address circuit 5.2.3 Y address circuit Figure 5-7 5.3 Oscillator Figure 5-9 5.9 Partial Display Mode 5.10 Screen Scroll 6. RESET 7. COMMAND (c) RDY timing (d) Serial interface 66 Preliminary Product Information S14797EJ3V7PM PD161620 (2/2) Edition/ Date This edition 3rd edition/ S14797EJ3V7PM00 Jul. 2001 Throughout Throughout p.1 p.2 p.3,4,5,6,7 p.8 p.12 - p.13 p.13 p.14 p.16 p.16 p.17 p.18 p.18 p.20 p.23 p.24 p.25 p.26 p.27 p.41 p.45 p.46 p.47, 48, 49, 50 p.51 p.51 p.51 p.52 p.53 to 61 p.62 p.63, 64 p.65 Page Previous edition Throughout Throughout p.1 p.2 p.3,4,5,6 p.7 p.10,11 p.11 p.12 p.12 p.13 p.15 p.15 p.15 p.17 p.18 p.20 p.20 p.20 p.21 - p.22 - p.36 p.37 p.38, 39 p.40 p.40 p.40 p.41 p.42 to 50 p.51 - - Type of revision Deletion Addition Modification Modification Modification Modification Modification Deletion Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Modification Addition Modification Addition Modification Modification Modification Modification Modification Addition Modification Modification Modification Addition Addition 384 output V8 to V15, VRH, VRL1, VRL2 Driver supply voltage, CPU interface (FEATURES) 1. BLOCK DIAGRAM 2. PIN CONFIGURATION, Table2-1 Pad Layout 3. PIN FUNCTIONS 4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS Note 2, 3, 4 5.1.1 Selection of interface type 5.1.2 Selection of data transfer mode 5.1.3 Parallel interface 5.1.4 Serial interface 5.1.5 Chip select 5.1.6 Wait control in parallel interface mode 5.2.3 Y address circuit Figure 5-7. PD161620 RAM addressing 5.4 Display Timing Generator 5.5 Common Adjustment Circuit 5.6 Square Wave Signal Generation Circuit 5.8 -Curve Correction Power Supply Circuit for Cases of Unbalanced Driving, Figure5-14 -Curve correction circuit Table5-7 -Curve correction circuit 5.9 Partial Display Mode, caution 5.11 Initialization Setting Sequence Example 6. RESET 7.1 Command List, Caution1 7.2 Command Explanation Power supply voltage for -curve correction (Absolute Maximum Ratings) Power supply voltage, Input voltage (Recommended Operating Conditions) Notes1, 2 (Recommended Operating Conditions) Electrical Specifications Each table (AC Characteristics) (e) Common 9. CONNECTION of PD161620, 161640, and 161660 10. EXAMPLE of PD161620 and CPU CONNECTION Description Location Preliminary Product Information S14797EJ3V7PM 67 PD161620 [MEMO] 68 Preliminary Product Information S14797EJ3V7PM PD161620 [MEMO] Preliminary Product Information S14797EJ3V7PM 69 PD161620 [MEMO] 70 Preliminary Product Information S14797EJ3V7PM PD161620 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Preliminary Product Information S14797EJ3V7PM 71 |
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